1. Field of the Invention
The present invention relates generally to integrated circuit design and, more specifically, to a method of completing the design of integrated circuits having embedded test structures.
2. Description of Related Art
As the design of integrated circuits continues to become more complex, it is becoming increasingly necessary to embed specialized test structures into circuit designs and develop specialized verification methodology. The addition of embedded test to a circuit is complex, particularly for large circuits. The circuit must be analyzed to identify sub-blocks which must be modified to receive embedded test features. The modified sub-blocks must be integrated into its parent block which must then be modified to access the test structures added to the sub-block. Some parent blocks may contain many sub-blocks. The test ready parent blocks are then inserted into a circuit top-level block which must then be prepared to access the test structures embedded in the blocks and sub-blocks. The test structures may include a number of test controllers of various types including, for example, logic test controllers, including one for each block in the circuit, phase lock loop controllers, memory test controllers and others.
After the circuit functional design has been completed and all test structures have been integrated into the circuit, the circuit must be prepared for sign-off to manufacturing. There is a need for a circuit sign-off flow or method for use with circuits in which embedded test structures have been integrated into a circuit design to ensure that the completed circuit can be properly verified as quickly, efficiently and accurately as possible.
The present seeks to provide a sign-off flow or method for use with circuits in which embedded test structures have been integrated to ensure that the completed circuit can be properly verified as quickly, efficiently and accurately as possible.
One aspect of the present invention is generally defined as a circuit sign-off method for use in verifying a circuit design having circuit modules with embedded test circuitry, comprising, for each circuit module, checking connectivity of embedded test circuitry; creating a verification configuration file; for a circuit module having logic test circuitry, checking the circuit module against scan design rules; and creating associated logic test vectors and signature; performing a timing analysis of the circuit module; creating a hand-off database containing files associated with each test structure embedded in the circuit module; creating circuit module top-level test benches for validating each mode of operation of each embedded test circuitry using parameters contained in the configuration file; simulating the embedded test circuitry by executing the test benches on a simulator; and creating manufacturing test patterns after all verification steps have been successfully completed and following optimization and layout of the circuit.